1. Field of the Invention
The present invention relates to an integrated circuit and method for testing memory on the integrated circuit.
2. Description of the Prior Art
It is becoming more and more common for integrated circuits to include embedded memory to allow rapid access to data by functional circuits provided on the integrated circuit. Whilst an integrated circuit may traditionally comprise a number of circuit components formed on a single die, it may also consist of circuit components distributed across multiple dies that are integrated together in a package using 3D integration technologies such as multi-chip modules, system in package, or through-silicon-vias.
As the use of embedded memory continues to increase, thorough testing and defect diagnosis has become a key requirement to ensure product quality and enhance product yield. Whilst embedded memory presents significant system performance and cost reduction advantages, it brings its own testing issues. Externally generated test vector style tests are not suitable for verifying embedded memory arrays for a number of reasons. Firstly, the time spent in the manufacturing test grows exponentially as the embedded memory die area increases, which often makes such test vector style testing too costly. Furthermore, it is sometimes not possible to create a set of vectors that can detect all possible types of memory defect.
A known technique which alleviates such problems is to provide the integrated circuit with a memory Built In Self-Test (BIST) mechanism. In simplistic terms, a memory BIST (MBIST) mechanism is an on-chip utility that enables the execution of a proven set of algorithmic style verification tests directly on the embedded memory. These tests can be executed at the design's full operating frequency to prove the memory operations and identify errors caused by silicon defects.
In accordance with one known technique, a separate BIST mechanism is provided for each embedded memory within the integrated circuit. However, as the number of memory circuits provided within the integrated circuit increases, such an approach results in the chip area devoted to testing becoming unacceptably large. Hence, techniques have been developed which enable the BIST mechanism to be shared amongst several embedded memories within the integrated circuit. One such technique is described in U.S. Pat. No. 4,969,148, where, as for example shown in FIGS. 6 and 7 of that document, a single MBIST mechanism is shared between a number of embedded RAM (Random Access Memory) blocks within the integrated circuit. As can be seen from those figures, this technique involves providing a two-input multiplexer assembly in association with the data in port of each RAM block.
In the example of FIG. 6 of U.S. Pat. No. 4,969,148, the RAM blocks are connected in a daisy chain arrangement, such that the data input line of RAM 1 is connected to the serial data out port of the MBIST mechanism, the data output line of RAM 1 is connected to the data input line of RAM 2, the data output line of RAM 2 is connected to the data input line of RAM 3 and the data output line of RAM 3 is connected to the serial data in port of the MBIST mechanism. When in the test mode, the MBIST mechanism can operate at the system clock speed and serially shifts test bits from its serial data out port through the sequence of RAM blocks via the associated multiplexer assemblies, with the output from the last RAM block being returned to the serial data in port of the MBIST mechanism. During this test process, the same address is provided to each of the RAM blocks in parallel. This arrangement for sharing the test circuitry simplifies the testing procedure since the three memories are treated as if they were one large memory. In accordance with an alternative embodiment shown in FIG. 7 of U.S. Pat. No. 4,969,148, a RAM select counter and associated “1 of 3” multiplexer is used to provide an arrangement where only of the memories is tested at a time.
U.S. Pat. No. 6,191,603 describes a modular embedded test system for use in integrated circuits. In accordance with this technique, a number of core modules are provided, and each core may possess BIST functions which can be activated using external commands. An access scan chain is provided for controlling tests performed on each core, and a separate data scan chain is provided to apply specific test vectors and observe their responses.
The article “An Effective Distributed BIST Architecture for RAMs” by M Bodoni et al, Proceedings of the IEEE European Test Workshop (ETW '00), describes a BIST architecture employing a single BIST processor used to test all the memories of the system, and a wrapper for each SRAM including standard memory BIST modules. The architecture employs a normal test scan chain (NTScan) and a results scan chain (Resscan), and commands for these two scan chains, along with synchronisation signals used to forward test primitives to the wrappers, are multiplexed within each wrapper to reduce routing overhead. March tests (or test algorithms) are applied one memory operation at a time, and as a result multiple operations cannot be applied at system clock speed.
As the number of memory units embedded within the integrated circuit increases, then this results in an increase in the complexity of the interface between those memory units and a shared BIST mechanism for those memory units. The known BIST mechanism sharing techniques become complex to manage as the number of memory units increase, and further lack flexibility with regard to the tests to be applied on each of the memory units.
Commonly owned co-pending U.S. patent application Ser. No. 11/270,818, the entire contents of which are hereby incorporated by reference, describes memory test circuitry which comprises a plurality of test wrapper units, each test wrapper unit being associated with a corresponding memory unit, and a test controller for controlling performance of a sequence of tests by communicating with each of the test wrapper units. Two different communication links are provided between the test controller and the test wrapper units. In particular, a first communication link connects each of the test wrapper units directly with the test controller, and allows first test data to be broadcast in parallel to all of the plurality of test wrapper units, the first communication link hence providing a very efficient mechanism for disseminating global test data required by each of the test wrapper units. Further, a second communication link is provided to connect each test wrapper unit in an ordered sequence with the test controller. The second communication link is used to output a sequence of blocks of second test data, where each block is received by one of the test wrapper units. Hence, device specific test data can be routed through the second communication link so as to allow each test wrapper unit to receive its own tailored test data.
Such an approach has been found to improve flexibility, since the use of both communication links provides flexibility in how the tests are set up for execution by each test wrapper unit. Further, the approach is readily scalable for increased numbers of memory units, allowing an arbitrary number of test wrapper units to be connected to a single controller.
However, such a memory BIST system, like most traditional memory BIST systems, is rigidly organised according to physical hierarchy or other physical constraints such as clock domains. This organisation naturally arises from attempts to reduce area and routing. The individual test wrapper units (also referred to herein as BIST modules) then need to be accessed according to this organisation. Accordingly, when developing test sequences to be executed, knowledge is required of the physical arrangement of the various test wrapper units so as to ensure that the correct test data is provided to the required test wrapper units.
Whilst the above mentioned U.S. patent application Ser. No. 11/270,818 allows certain registers within the separate test wrapper units to be written to in a broadcast mode via the first communication link, the use of this link is only appropriate when it is desired to target all of the test wrapper units in the system. In order to target individual test wrappers, the serial JTAG-style approach provided by the second communications link needs to be used. When using the second communications link, individual registers in each of the BIST wrapper units can be concatenated together into a single long shift register accessed via the second communications link. This long shift register can be shortened by putting some components into bypass, thereby replacing the relevant register of the bypassed wrapper unit with a single flip-flop. Whilst this can shorten the overall length of the long shift register formed by the concatenation of the individual registers, one command is required to bypass each BIST wrapper unit, and knowledge about the type of memory tested by each BIST wrapper unit must be maintained by the test equipment and the test program.
Further, if the overall result of the test is required using the above described mechanism, data would need to be shifted out from all of the relevant shift registers within the BIST wrapper units and aggregated by the test equipment and test program. If the result for a subset of memories is required using such a mechanism, data would be shifted out from all of the shift registers (possibly with unneeded data values bypassed) and then aggregated by the test equipment and test program based on information maintained by the test program about which memories are in the subset of memories of interest.
As a result, when using such prior art techniques, the test program needs to be written specifically for each integrated circuit, and if the integrated circuit changes, the test program must be recreated.
Accordingly, it would be desirable to provide an improved mechanism for testing memory units provided on an integrated circuit, which allows test programs to be developed without knowledge of the exact layout of the memory units within the integrated circuit.